1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a high voltage metal oxide semiconductor device.
2. Description of the Related Art
As the dimension of metal oxide semiconductor device continues to shrink, the resulting shorter channel length leads to an increase in the operating speed of the transistor. However, other problems related to the shorter channel grouped under the so-called ‘short channel effect’ intensify. If the applied voltage remains unchanged but the transistor channel length is reduced, the energy of the electrons inside the channel will increase due to the acceleration by the electric field according to the basic formula: electric field=voltage/length. As a result, the chance of electrical breakdown will increase. Furthermore, the increase in the intensity of the electric field will also lead to an increase in the energy of the electrons within the channel and ultimately result in an electrical breakdown.
In high power devices, double-diffused metal oxide semiconductor (DMOS) is an important device capable of handling high input voltage. In general, the DMOS device can be categorized into lateral double-diffused MOS (LDMOS) and vertical double-diffused MOS (VDMOS).
FIG. 1 is a schematic cross-sectional view of a conventional LDMOS. As shown in FIG. 1, the LDMOS device mainly comprises a substrate 100, a field oxide layer 102, a gate dielectric layer 104, a gate 106, an N-type drift region 108, an N-type drain region 110, a P-type well 112 and an N-type source region 114. The substrate 100 is an N-type substrate (or a P-type substrate). The field oxide layer 102 is disposed in the substrate 100. The gate dielectric layer 104 is disposed in the substrate 100 adjacent to the field oxide layer 102. The gate 106 is disposed on the gate dielectric layer 104 and a portion of the field oxide layer 102. The N-type drift region 108 is disposed in the substrate 100 under the field oxide layer 102. The N-type drain region 110 is disposed in the substrate 100 on one side of the gate 106 close to the field oxide layer 102. The P-type well 112 is disposed in the substrate 100 on another side of the gate 106. The N-type source region 114 is disposed in the P-type well 112.
To meet the demand in high voltage applications, the N-type drain region 108 of the LDMOS device is doped lightly to reduce dopant concentration. However, this method has limited capacity for increasing the operating voltage. Moreover, the driving current will be reduced as well.
FIG. 2 is a schematic cross-sectional view of a conventional VDMOS device. As shown in FIG. 2, the VDMOS device mainly comprises a substrate 200, an N-type epitaxial layer 202, a gate dielectric layer 204, a gate 206, an N-type source region 208, a P-type well 210 and an insulating layer 212. The substrate 200 is an N-type substrate. The N-type epitaxial layer 202 is disposed on the substrate 200. The gate dielectric layer 204 is disposed on the N-type epitaxial layer 202. The gate 206 is disposed on the gate dielectric layer 204. The N-type source region 208 is disposed in the P-type well 210 on each side of the gate 206. The insulating layer 212 covers the gate 206.
In the VDMOS device, the variation in the equipotential between neighboring P-type wells 210 is rather large. Hence, the breakdown voltage of the VDMOS device will be reduced. In fact, the highest operating voltage is in the vicinity between 60˜100V, which is a significant limitation on power applications requiring a high operating voltage.
The conventional DMOS device, whether it is a LDMOS or a VDMOS device, has limited capacity for increasing its breakdown voltage. Furthermore, the high ON-resistance (RON) of a conventional DMOS device is also a significant problem waiting to be resolved.